Paper Title:
Hybrid Reconfigurable PC Add-on Card for Parallel Image Processing
  Abstract

Specific hardware solutions are always faster than programmable architectures. But dedicated architectures have the inherent disadvantage of inflexibility. Changes in the algorithm or extensions of the application are handled easily by programmable architectures. The approach discussed here involves a hardware-software co-design to optimize on performance and programmability. The architecture houses two SHARC processors to aid in parallelizing the image processing algorithms, and a reconfigurable FPGA which may be configured on the fly to execute any of the real-time algorithms as desired. The functional memory would consist of pre-designs (FPGA based) of certain objects, each of which could be used to configure an FPGA to perform a particular function.

  Info
Periodical
Chapter
Chapter 23: Computer-Aided Design, Manufacturing, and Engineering
Edited by
Wu Fan
Pages
5057-5062
DOI
10.4028/www.scientific.net/AMM.110-116.5057
Citation
A. Ravi, E. E.A. Moorthy, D. Vidya, G.M. Kumar, "Hybrid Reconfigurable PC Add-on Card for Parallel Image Processing", Applied Mechanics and Materials, Vols. 110-116, pp. 5057-5062, 2012
Online since
October 2011
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Price
$32.00
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