Paper Title:
Design of Quaternary Half Adder Using Hybrid SETMOS Cell
  Abstract

Adder is one of the important arithmetic units in computers. In this paper, we investigate the implementation of quaternary half adder based on multiple-valued (MV) logic gates using single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. We use hybrid SETMOS universal literal gate which has been proposed by Mahapatra and Ionesco. We apply two 4-radix inputs to the proposed quaternary half adder and obtain sum and carry outputs. The logic operation of the proposed quaternary half adder is verified by using HSPICE simulator. Moreover we compare the performance of our proposed quaternary half adder with the performance of a quaternary half adder based on MOS technology.

  Info
Periodical
Chapter
Chapter 23: Computer-Aided Design, Manufacturing, and Engineering
Edited by
Wu Fan
Pages
5085-5089
DOI
10.4028/www.scientific.net/AMM.110-116.5085
Citation
K. Feizi, A. Shahhoseini, "Design of Quaternary Half Adder Using Hybrid SETMOS Cell", Applied Mechanics and Materials, Vols. 110-116, pp. 5085-5089, 2012
Online since
October 2011
Export
Price
$32.00
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