Paper Title:
A High Efficiency CMOS Power Amplfieir with a Diode Linearizer and Voltage Combining Transformers
  Abstract

This paper proposes a high efficiency power amplifier with a diode linearizer and voltage combining transformers in a standard 0.13-μm TSMC CMOS technology. The 3-D simulated transformer adopts multi-finger architecture which provides low insertion loss and allows high current capacity on the transformer. With the 4 differentially cascaded connected multi-finger transformers, the amplifier delivers more than 1W output power under 1.8 V supply condition. To enhance linearity of the power amplifier, the diode configuration bias circuit is used in this paper. With all integration of transformers, balun, diode bias circuits and same 4 diff-amps, the prototype Class AB Power Amplifier shows 32dBm saturation power at 2.4 GHz. Due to the diode linearizer the output P1dB is 30.8 dBm with 28 % Power Added Efficiency.

  Info
Periodical
Chapter
Chapter 24: Semiconductor Materials Manufacturing
Edited by
Wu Fan
Pages
5500-5504
DOI
10.4028/www.scientific.net/AMM.110-116.5500
Citation
K. J. Kim, T. H. Lim, S.H. Park, K. H. Ahn, "A High Efficiency CMOS Power Amplfieir with a Diode Linearizer and Voltage Combining Transformers", Applied Mechanics and Materials, Vols. 110-116, pp. 5500-5504, 2012
Online since
October 2011
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Price
$32.00
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