Paper Title:
A Robust High Density 7T Subthreshold SRAM Bitcell with Partial Dynamic Threshold Voltage Connection Scheme
  Abstract

Combined with partial dynamic threshold MOSFET connection scheme, a high density 7T subthreshold SRAM bitcell operating at supply voltage of 200 mV is proposed in this paper. Dual write and single read ensures high read static noise margin of the SRAM bitcell without expense of writability degradation. The 7T SRAM exhibits robust efficiency, making the design less vulnerable to process variation. Compared to the referenced 6T and the 8T SRAM bitcell, the proposed bitcell has four aspects of improvement: (1) 5.1% and 6.1% larger hold margin, (2) 80.6% and 85.5% of standard deviation, (3) 50% and 18% reduction of area (at 200 mV), and (4) 16X and 32X bitcells per bitline. To our best knowledge, the area penalty of proposed SRAM is the smallest with robustness and functionality of subthreshold SRAM achieved.

  Info
Periodical
Chapter
Chapter 3: Advanced Manufacturing Technology (1)
Edited by
Dongye Sun, Wen-Pei Sung and Ran Chen
Pages
1279-1285
DOI
10.4028/www.scientific.net/AMM.121-126.1279
Citation
J. Yang, M. Q. Qiu, K. Huang, N. Bai, "A Robust High Density 7T Subthreshold SRAM Bitcell with Partial Dynamic Threshold Voltage Connection Scheme", Applied Mechanics and Materials, Vols. 121-126, pp. 1279-1285, 2012
Online since
October 2011
Export
Price
$32.00
Share

In order to see related information, you need to Login.

In order to see related information, you need to Login.

Authors: Na Bai, Rui Xing Li, Zhan Li Gong, Shou Biao Tan
Chapter 3: Advanced Manufacturing Technology (1)
Abstract:Simulation results illustrate that there is an optimum-energy supply voltage point (Vopt) for SoC. And these voltage points normally lie in...
1332
Authors: Jie Li, Zhuang Zhang, Wei Wei Shan
Chapter 2: Advanced Manufacturing Systems and Equipment
Abstract:As semiconductor technology develops toward very deep submicron or even nanometer, power consumption per unit area increases dramatically....
467
Authors: Jun Yang, Na Bai, Wei Qi Wu, Wei Wei Shan, Zhi Kuang Cai
Chapter 2: Advanced Manufacturing Systems and Equipment
Abstract:In this paper, a SRAM array targeting IBM 130nm CMOS technology is proposed for ultra dynamic voltage scaling (UDVS) application with better...
450
Authors: Ming Qiang Qiu, Na Bai, Jian Meng, Jun Ning Chen
Chapter 3: System Analysis and Industrial Engineering
Abstract:The SRAM applied to dynamic voltage scaling systems has a problem that the differential voltage of the bitlines (ΔVBL) increases...
416
Authors: Bai Tao Lv, Rui Xing Li, Jiafeng Zhu, Na Bai, Xiu Long Wu
Chapter 6: Mechatronics
Abstract:This paper describes a circuit which can enhance the robustness of the subthreshold 6T SRAM bitcell. The proposed circuit can dynamically...
1001