Paper Title:
A New P-Type Clocked Adiabatic Logic for Nanometer CMOS Processes with Gate Oxide Materials
  Abstract

Leakage current is becoming a significant contributor to power dissipations in nanometer CMOS circuits due to the scaling of oxide thickness. This paper proposes a new P-type clocked adiabatic logic (P-CAL) to reduce gate leakage based on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones in nanometer CMOS processes using gate oxide materials. Based on the power dissipation models of adiabatic circuits, the estimation technology for the active leakage dissipations of P-CAL circuits is proposed. The active leakage dissipations are estimated by testing total leakage dissipations with additional load capacitances using SPICE simulations. Compared to N-type clocked adiabatic logic (N-CAL) circuits, the total power and leakage power dissipation of P-type CAL circuits are reduced greatly.

  Info
Periodical
Edited by
Honghua Tan
Pages
1930-1936
DOI
10.4028/www.scientific.net/AMM.29-32.1930
Citation
J. P. Hu, L. F. Ye, L. Su, "A New P-Type Clocked Adiabatic Logic for Nanometer CMOS Processes with Gate Oxide Materials", Applied Mechanics and Materials, Vols. 29-32, pp. 1930-1936, 2010
Online since
August 2010
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