With rapid technology scaling, the leakage dissipation is becoming a major source in CMOS circuits because of the increasing sub-threshold and gate leakage current in nanometer CMOS processes. This paper presents an adiabatic register file based on improved CAL (Clocked Adiabatic Logic) using MTCMOS power-gating and drowsy cache techniques to reduce both sub-threshold leakage and gate oxide leakage current dissipations. A 32 X 32 single-phase adiabatic register file are verified using HSPICE. BSIM4 model is adopted to reflect leakage currents in nanometer CMOS processes with gate oxide materials. Simulation results show that leakage losses are greatly reduced.