With rapid technology scaling down, the energy dissipation of nanometer CMOS circuits is becoming a major concern, because of the increasing sub-threshold leakage in nanometer CMOS processes. This paper introduces a dual threshold CMOS (DTCMOS) technique for CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The method to size the transistors of the dual-threshold CPAL gates is also discussed. A full adder using dual-threshold CPAL circuits is realized using 45nm BSIM4 CMOS model. HSPICE simulation results show that leakage dissipations of the CPAL full adder with DTCMOS techniques are reduced compared with the basic CPAL one.