Paper Title:
The Design and Simulation of a CMOS Digital PLL
  Abstract

In this paper, the charge-pump PLL structure is well analyzed. By using top-down method, the digital PLL is designed from frequency phase detector, charge pump, loop filter, VCO to frequency divider. Based on 0.5μm CMOS mixed signal process, the schematic and layout design is finished on Cadence IC 5.1.4.1, and Hspice is used for the simulation. The layout verification and parasitic extraction is completed on industry mainstream Calibre software. Simulation results show that the digital PLL is with a 100MHz center frequency, the locking range is between 20MHz~60MHz, the locking time is less than 1.5μs, and phase noise is -105dBc/Hz. The design has implemented the digital signal lock function and it can be used as an IP hard core in the clock recovery of communication systems and frequency synthesis of digital systems.

  Info
Periodical
Edited by
Zhixiang Hou
Pages
1227-1230
DOI
10.4028/www.scientific.net/AMM.48-49.1227
Citation
K. Y. Wang, Z. N. Tang, T. Ge, "The Design and Simulation of a CMOS Digital PLL", Applied Mechanics and Materials, Vols. 48-49, pp. 1227-1230, 2011
Online since
February 2011
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Price
$32.00
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