A highly efficient, single-port SRAM-based loop filter based on H.264 is presented. Hybrid edge filtering order, efficient memory organization for both on-chip SRAM and transposition buffers, and five-stage pipeline architect are adopted in the design. Efficient transposition buffer organization reduces the gate counts and the memory access times. By using hybrid edge filtering order and alternating output memory update scenario, zero stall cycle in pipeline flow is realized. To balance on-chip memory size and bus bandwidth, the design can be configured to operate in on-chip memory and off-chip memory modes.