Paper Title:
Fault Tolerance Design by Accurate SER Estimation Based on Ensemble Transform Matrix
  Abstract

With development of CMOS process, the minimum lithographic feature has now scaled down to regime of nano-scale. Integrated circuits (ICs) are becoming increasingly susceptible to uncertainty caused by soft errors, inherently probabilistic devices, and manufacturing variability. With all kinds of faults and errors, soft error is the most common and widespread. The different design methodology can reach different soft error tolerance ability, so we must find a way to estimate the soft error rate (SER) efficiently to make the design more fault tolerant. In this paper, we propose and investigate the ensemble transform matrix model. We show that the model can describe the actual nano-scale circuit performance. We also propose criteria to evaluate the circuits’ soft error tolerance capability. Simulation shows that the proposed ensemble transform matrix model is effective and suitable for CAD tools development in nano-scale circuit and system design.

  Info
Periodical
Advanced Materials Research (Volumes 108-111)
Edited by
Yanwen Wu
Pages
347-352
DOI
10.4028/www.scientific.net/AMR.108-111.347
Citation
C. H. Yu, "Fault Tolerance Design by Accurate SER Estimation Based on Ensemble Transform Matrix", Advanced Materials Research, Vols. 108-111, pp. 347-352, 2010
Online since
May 2010
Authors
Export
Price
$32.00
Share

In order to see related information, you need to Login.

In order to see related information, you need to Login.

Authors: Yang Bo Wu, Jian Ping Hu, Hong Li
Abstract:In deep sub-micro CMOS process, the leakage power is becoming a significant proportion in power dissipation. Hence, estimating the leakage...
625
Authors: Chang Hong Yu
Abstract:As the transistor sizes continue to shrink, quantum effects will significantly affect the circuit behavior. The inherent unreliability of...
87
Authors: Jing Hu, Dian Zhong Wen
Chapter 3: Active Materials, Mechanics and Behavior
Abstract:A new technique is presented for online test with some garbage lines in reversible circuits. Firstly, testable structures for reversible...
337
Authors: Xiao Hui Hu, Guo Qiang Hang, Yang Yang, Xiao Hu You
Chapter 3: Power Systems, Electronics and Microelectronics, Embedded and Integrated Systems, Communication
Abstract:The dynamic circuit technology can decrease the whole power consumption, and the Floating-gate technology can simplify the circuit structure,...
1323