With development of CMOS process, the minimum lithographic feature has now scaled down to regime of nano-scale. Integrated circuits (ICs) are becoming increasingly susceptible to uncertainty caused by soft errors, inherently probabilistic devices, and manufacturing variability. With all kinds of faults and errors, soft error is the most common and widespread. The different design methodology can reach different soft error tolerance ability, so we must find a way to estimate the soft error rate (SER) efficiently to make the design more fault tolerant. In this paper, we propose and investigate the ensemble transform matrix model. We show that the model can describe the actual nano-scale circuit performance. We also propose criteria to evaluate the circuits’ soft error tolerance capability. Simulation shows that the proposed ensemble transform matrix model is effective and suitable for CAD tools development in nano-scale circuit and system design.