Paper Title:
An Adiabatic Register Based on Dual Threshold Leakage Reduction Technique
  Abstract

This paper introduces a leakage reduction technique using dual threshold CMOS in CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The leakage current source of the CPAL circuits is analyzed under nanometer CMOS processes. A 32 X 32 CPAL register file is demonstrated using the proposed dual threshold technique. In the proposed register file, the logic gates on critical path use low threshold transistors, while the other logic gates use dual threshold technique to reduce their leakage dissipations. All circuits are verified using HSPICE in different processes, threshold voltages, and operation frequencies, and BSIM4 model is adopted to reflect the leakage currents. Simulation results show that leakage losses are obviously reduced both in active mode and idle mode.

  Info
Periodical
Advanced Materials Research (Volumes 121-122)
Edited by
Donald C. Wunsch II, Honghua Tan, Dehuai Zeng, Qi Luo
Pages
148-153
DOI
10.4028/www.scientific.net/AMR.121-122.148
Citation
J. P. Hu, X. Y. Yu, X. L. Sheng, "An Adiabatic Register Based on Dual Threshold Leakage Reduction Technique", Advanced Materials Research, Vols. 121-122, pp. 148-153, 2010
Online since
June 2010
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Price
$32.00
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