Paper Title:
Leakage Reduction of Improved CAL Registers Using MTCMOS Power-Gating Scheme in Nanometer CMOS Processes
  Abstract

With rapid technology scaling, the leakage dissipation that begins to replace dynamitic dissipation is becoming a major source in CMOS circuits because of the increasing sub-threshold leakage current in nanometer CMOS processes. This paper introduces a MTCMOS power-gating technique, which is used for an adiabatic register file based on improved CAL (Clocked Adiabatic Logic) to reduce leakage dissipation in sleep mode. A 32 X 32 single-phase adiabatic register file are verified using HSPICE in different processes, threshold voltage, and active ratios, and BSIM4 model is adopted to reflect the leakage currents. Simulation results show that leakage losses are greatly reduced.

  Info
Periodical
Advanced Materials Research (Volumes 121-122)
Edited by
Donald C. Wunsch II, Honghua Tan, Dehuai Zeng, Qi Luo
Pages
281-286
DOI
10.4028/www.scientific.net/AMR.121-122.281
Citation
J. G. Zhu, J. P. Hu, "Leakage Reduction of Improved CAL Registers Using MTCMOS Power-Gating Scheme in Nanometer CMOS Processes", Advanced Materials Research, Vols. 121-122, pp. 281-286, 2010
Online since
June 2010
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Price
$32.00
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