Paper Title:
Through Silicon Vias (TSVs) Technology for MEMS Packaging
  Abstract

Through silicon vias (TSVs) provide advanced vertical interconnections solutions for system-in-package (SiP) (such as chip to chip, chip to wafer, and wafer to wafer stacking), wafer-level packaging, interposer packaging. At present the shortest electrical path (vertical electrical feed through) between two sides of a silicon chip is one of the important applications. In order to achieve high density and high performance package, TSVs technology has been developed. And for three-dimensional (3D) MEMS (Microelectromechanical System) packaging, TSVs are the most important enabling technology. In this paper, some advantages of TSVs technology are described, and process flow of TSVs module is introduced firstly. Subsequently, a novel electricity test method of Non-Ideal Planes for TSVs is introduced. Finally, many critical issues and challenges of TSVs are reviewed.

  Info
Periodical
Advanced Materials Research (Volumes 154-155)
Edited by
Zhengyi Jiang, Xianghua Liu and Jinglong Bu
Pages
1695-1698
DOI
10.4028/www.scientific.net/AMR.154-155.1695
Citation
K. L. Pan, J. Liu, J. P. Wang, J. Huang, "Through Silicon Vias (TSVs) Technology for MEMS Packaging", Advanced Materials Research, Vols. 154-155, pp. 1695-1698, 2011
Online since
October 2010
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Price
$32.00
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