Paper Title:
P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits
  Abstract

With rapid technology scaling, the proportion of the leakage power catches up with dynamic power gradually. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. This paper presents adiabatic sequential circuits using P-type complementary pass-transistor adiabatic logic circuit (P-CPAL) to reduce the gate-leakage power dissipations. A practical sequential system with a mode-10 counter is demonstrated using the P-CPAL scheme. All circuits are simulated using HSPICE under 65nm and 90nm CMOS processes. Simulations show that the mode-10 counter using P-CPAL circuits obtains significant improvement in terms of power consumption over the traditional N-type CPAL counterparts.

  Info
Periodical
Edited by
Dehuai Zeng
Pages
155-161
DOI
10.4028/www.scientific.net/AMR.159.155
Citation
J. T. Jiang, Y. Zhang, J. P. Hu, "P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits", Advanced Materials Research, Vol. 159, pp. 155-161, 2011
Online since
December 2010
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