Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. The leakage dissipation caused by leakage currents is becoming an increasingly important fraction of the total power dissipation in nanometer integrated circuits. To decrease leakage power dissipations is becoming more and more important in micro-power nanometer circuits. An improved CAL register file using DTCMOS (Dual-Threshold Technique) for reducing leakage dissipations in active mode is addressed in this paper. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE at 45nm CMOS process. Simulation results show that the register file with dual-threshold can reduce about 15.6% power dissipations.