In designing an FPGA based on a 0.5 micron SOI-CMOS technology we experienced a crucial task of providing a robust programmable interconnection network to drive long-line and global signals through the entire chip. The performance and signal integrity of these signals are challenged by the variation in the process as well as the signal driving condition of the individual mapped circuits. In this paper, we focus on the design of an efficient long-line signal interconnect network targeting for high speed and low power consumption of the circuit operation in a tile-based FPGA. The design and verification of the long-line with booster in the channels and the clock network circuitry are described in details. The comparison of the simulation and measured signal timing data is reported.