Paper Title:
Design and Verification of Interconnection Network in an SOI-Based FPGA
  Abstract

In designing an FPGA based on a 0.5 micron SOI-CMOS technology we experienced a crucial task of providing a robust programmable interconnection network to drive long-line and global signals through the entire chip. The performance and signal integrity of these signals are challenged by the variation in the process as well as the signal driving condition of the individual mapped circuits. In this paper, we focus on the design of an efficient long-line signal interconnect network targeting for high speed and low power consumption of the circuit operation in a tile-based FPGA. The design and verification of the long-line with booster in the channels and the clock network circuitry are described in details. The comparison of the simulation and measured signal timing data is reported.

  Info
Periodical
Edited by
Dehuai Zeng
Pages
532-537
DOI
10.4028/www.scientific.net/AMR.159.532
Citation
Y. Zhao, X. W. Han, L. H. Wu, F. Yu, "Design and Verification of Interconnection Network in an SOI-Based FPGA", Advanced Materials Research, Vol. 159, pp. 532-537, 2011
Online since
December 2010
Export
Price
$32.00
Share

In order to see related information, you need to Login.

In order to see related information, you need to Login.

Authors: Shih Han Lin, Shu Jung Chen, Chih Hsiung Shen
Abstract:A new modified CMOS buffer amplifier with rail-to-rail input and output range is proposed by TSMC 0.35μm 2P4M process at 3.3V supply. The...
3765
Authors: Bin Bin Lu, Jian Ping Hu
Abstract:With rapid technology scaling down, the energy dissipation of nanometer CMOS circuits is becoming a major concern, because of the increasing...
55
Authors: Jian Chen, Kai Xiong Su, Xiu Zhi Yang, Rong Hua Lin
Abstract:In the demand of compounding transmission with SD and HD programs, based on analyzing two kind of multiplexing models’ characteristic with...
233
Authors: Xin Jin, Jian Su, Chang Hai Yang
Chapter 8: Advanced Decisions for Automatic Manufacturing
Abstract:In order to buffer the randomness failure of automated production car body shop is growing tendency to set buffer between lines to solve this...
1666
Authors: Jun Yang, Hong Ye Li, Long Liu
Chapter 11: Modern Electronic, Circuit Technology, Electrical and Power Engineering
Abstract:The digital clock is a clock designed by digital circuit. Now, there are some limitations in the use and regulation of the digital clock in...
1266