To meet the needs of a variety of applications, and solve the problem that some existing transmission equipment and terminal equipment can not be interconnected, a new fast method for clock recovery in digital communication is presented. Based on the basic theory of digital multiplexing technology, using FPGA large-scale integration technology, the design of the new system in asynchronous multiplexing at low rate is realized. In this system, 1 to 8 branchs low-speed data can be adaptive data multiplexing , and multi-frame structure can be set discretionarily. The design process and the realizing process to be adaptive are elaborated in this paper. Finally, test indicators are given, which meet the expected designing requirements.