Paper Title:
A New Clock Synchronization Method for Multi-FPGA Systems
  Abstract

A novel clock synchronization scheme is proposed in this paper, which smartly takes the advantages of the inner delay-locked loop(DLL) to compensate for the delay generated by board-level feedback, combining with conventional external clock tree scheme to achieve the system clock synchronization.

  Info
Periodical
Advanced Materials Research (Volumes 204-210)
Edited by
Helen Zhang, Gang Shen and David Jin
Pages
907-910
DOI
10.4028/www.scientific.net/AMR.204-210.907
Citation
C. C. Zhang, L. S. Yang, X. P. Hu, H. Yang, P. Li, "A New Clock Synchronization Method for Multi-FPGA Systems", Advanced Materials Research, Vols. 204-210, pp. 907-910, 2011
Online since
February 2011
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