Paper Title:
MOSFET Performance Manufactured on <100> Silicon Wafer Using CESL Strain Technology with Temperature Effect
  Abstract

Tensile and compressive silicon nitride films as contact etch stop layers (CESL) are deposited on the poly-gate of N/PMOSFETs providing the strains to the channels. Different strained engineering technologies, previously determined by various processes and firmly verified by testing, set up different environments for carriers to transport. It is quite reasonably conclusive that compressive CESL benefits NMOS devices more while tensile CESL favors PMOS devices more. This phenomenon may be also true as the temperature effects are taken into concern. Higher temperatures tend to thermally disturb the carriers making the effective mass modified. The consistency and the known techniques can be applied to the nano-node generation development.

  Info
Periodical
Advanced Materials Research (Volumes 287-290)
Chapter
Other related topics
Edited by
Jinglong Bu, Pengcheng Wang, Liqun Ai, Xiaoming Sang, Yungang Li
Pages
2974-2977
DOI
10.4028/www.scientific.net/AMR.287-290.2974
Citation
M. C. Wang, H. C. Yang, W. S. Liao, "MOSFET Performance Manufactured on <100> Silicon Wafer Using CESL Strain Technology with Temperature Effect", Advanced Materials Research, Vols. 287-290, pp. 2974-2977, 2011
Online since
July 2011
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