Paper Title:
High-Speed LMS Algorithm’s Design and Implementation Based on FPGA
  Abstract

This Paper Proposes a Kind of High-Speed Hardware Implementation Method by the Adaptive Equalizer (LMS Equalizer) Based on MSE Criteria. this Design First Makes Full Use of FPGA Internal Hardware on Time-Multiplier (DSP48Es), and Uses the High Throughput of the Streaming Design. then Reoccupy Matlab Software Simulation and Fixed Point Design, Finally Realized ML506 Development Board in Hardware Association Simulation. Experimental Proof, both the Simulation Results Are Consistent, and it Shows that the Proposed Algorithm Is Feasibility and Efficiency, and Has a High Application Value.

  Info
Periodical
Advanced Materials Research (Volumes 301-303)
Chapter
Chapter 2: Measuring and Testing Techniques
Edited by
Riza Esa and Yanwen Wu
Pages
1157-1161
DOI
10.4028/www.scientific.net/AMR.301-303.1157
Citation
J. J. Liang, J. M. Gao, W. X. Ling, "High-Speed LMS Algorithm’s Design and Implementation Based on FPGA", Advanced Materials Research, Vols. 301-303, pp. 1157-1161, 2011
Online since
July 2011
Keywords
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Price
$32.00
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