Paper Title:
A Vernier Delay Line for Time Interval Measurement
  Abstract

This paper presents a Vernier Delay Line (VDL) for time interval measurement. A dedicated multiplexer is inserted into each stage of the proposed VDL. As a result, the D-flip-flops in each stage can be served as a large delay cell as well as a traditional arbiter. Moreover, the proposed interface circuit can save time residue out for further fine granularity measurement. Experimental results show that the proposed VDL achieves a 30ns measurement range with 6600 transistors.

  Info
Periodical
Advanced Materials Research (Volumes 301-303)
Chapter
Chapter 2: Measuring and Testing Techniques
Edited by
Riza Esa and Yanwen Wu
Pages
995-1000
DOI
10.4028/www.scientific.net/AMR.301-303.995
Citation
X. G. Wang, F. Wang, H. G. Yang, "A Vernier Delay Line for Time Interval Measurement", Advanced Materials Research, Vols. 301-303, pp. 995-1000, 2011
Online since
July 2011
Export
Price
$32.00
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