Paper Title:
Ternary Logic Dynamic CMOS Comparators
  Abstract

In this paper, a new method of ternary logic circuit design is developed. It’s proposed that two types of static ternary CMOS comparators and three types of dynamic CMOS comparators, designed by new method, with low transistor count, high speed and low power consumption. The proposed comparators are the rearrangement and reordering of transistors in the evaluation block of a dynamic cell. These ternary comparators can be used as equality comparators, mutual comparators and zero/one/two detectors, which are widely used in build in self test and memory testing.

  Info
Periodical
Advanced Materials Research (Volumes 317-319)
Chapter
Microelectronic Technology
Edited by
Xin Chen
Pages
1177-1182
DOI
10.4028/www.scientific.net/AMR.317-319.1177
Citation
X. Y. Jin, C. Li, J. B. Liu, X. F. Jiang, X. B. Zeng, "Ternary Logic Dynamic CMOS Comparators", Advanced Materials Research, Vols. 317-319, pp. 1177-1182, 2011
Online since
August 2011
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Price
$32.00
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