Paper Title:
Circuitry Design Feature of Stages with High-Gain Coefficient on Field-Effect Transistors
  Abstract

The feature of implementing of loops with self-compensation of CMOS transistors differential resistance in the gain stages is reviewed. Shown that these compensation loops reduce the parametric sensitivity of the stage and the transistors output capacitance influence on a range of operating frequencies. А set of loops of cancellation of the CMOS transistors parasitic parameters influence on stage cutoff frequency was proposed. The conclusions were made. An example of cost-stage high gain was given.

  Info
Periodical
Chapter
Chapter 2: Mechanical Engineering, Control Engineering and Materials Engineering
Edited by
Jun Hu and Qi Luo
Pages
589-596
DOI
10.4028/www.scientific.net/AMR.320.589
Citation
S. Krutchinsky, V. Bespyatov, A. Korolev, E. Zhebrun, A. Zolotarev, "Circuitry Design Feature of Stages with High-Gain Coefficient on Field-Effect Transistors", Advanced Materials Research, Vol. 320, pp. 589-596, 2011
Online since
August 2011
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Price
$32.00
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