The design of a high speed programmable frequency divider for fractional-N frequency synthesizer is presented. The programmable divider consists of a divide-by-4/5 dual-modulus prescaler, a 5-bit programmable counter, and a 2-bit swallow counter. A new scheme of reload operation is adopted to reduce the propagation delay of the critical path. The triggering signal for the two counters is selected carefully to mitigate the timing requirement of the mode control signal. The divider is designed in 0.18 um CMOS process. Its division ratio (DR) covers the range from 12 to 127. Post-layout simulations show it can work up to 5 GHz under 1.8 V power supply, while consuming only 9 mW and occupying an area of about 0.06 mm2.