Paper Title:
Design and Implementation of a Multi-Channel HDLC Protocol Controller Based on FPGA
  Abstract

To transmit and receive data over any network successfully, a protocol is required to manage the flow. High-level Data Link Control (HDLC) protocol is defined in Layer 2 of OSI model and is one of the most commonly used Layer 2 protocol. HDLC supports both full-duplex and half-duplex data transfer. In addition, it offers error control and flow control. Currently on the market there are many dedicated HDLC chips, but these chips are neither of control complexity nor of limited number of channels. This paper presents a new method for implementing a multi-channel HDLC protocol controller using Altera FPGA and VHDL as the target technology. Implementing a multi-channel HDLC protocol controller in FPGA offers the flexibility, upgradability and customization benefits of programmable logic and also reduces the total cost of every project which involves HDLC protocol controllers.

  Info
Periodical
Advanced Materials Research (Volumes 383-390)
Chapter
Chapter 27: Semiconductor Materials Manufacturing
Edited by
Wu Fan
Pages
6840-6845
DOI
10.4028/www.scientific.net/AMR.383-390.6840
Citation
Y. H. Gu, W. Huang, Q. L. Yang, "Design and Implementation of a Multi-Channel HDLC Protocol Controller Based on FPGA", Advanced Materials Research, Vols. 383-390, pp. 6840-6845, 2012
Online since
November 2011
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Price
$32.00
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