Paper Title:
Materials Science Issues for the Fabrication of Nanocrystal Memory Devices by Ultra Low Energy Ion Implantation
  Abstract

Nanocrystal memories are attractive candidate for the development of non volatile memory devices for deep submicron technologies. In a nanocrystal memory device, a 2D network of isolated nanocrystals is buried in the gate dielectric of a MOS and replaces the classical polysilicon layer used in floating gate (flash) memories. Recently, we have demonstrated a route to fabricate these devices at low cost by using ultra low energy ion implantation. Obviously, all the electrical characteristics of the device depend on the characteristics of the nanocrystal population (sizes and densities) but also on their exact location with respect to the gate and channel of the MOS transistor. It is the goal of this paper to report on the main materials science aspects of the fabrication of 2D arrays of Si nanocrystals in thin SiO2 layers and at tunable distances from their SiO2/interfaces.

  Info
Periodical
Defect and Diffusion Forum (Volumes 258-260)
Edited by
Andreas Öchsner and José Grácio
Pages
531-541
DOI
10.4028/www.scientific.net/DDF.258-260.531
Citation
A. Claverie, C. Bonafos, G. B. Assayag, S. Schamm, N. Cherkashin, V. Paillard, P. Dimitrakis, E. Kapetenakis, D. Tsoukalas, T. Muller, B. Schmidt, K.H. Heinig, M. Perego, M. Fanciulli, D. Mathiot, M. Carrada, P. Normand, "Materials Science Issues for the Fabrication of Nanocrystal Memory Devices by Ultra Low Energy Ion Implantation", Defect and Diffusion Forum, Vols. 258-260, pp. 531-541, 2006
Online since
October 2006
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