Paper Title:
Charge Trap Mechanism in Hybrid Nanostructured (YMnO3) Metal-Oxide-Semiconductor (MOS) Devices
  Abstract

Hybrid nanostructured Metal Oxide Semiconductor (MOS) capacitor was fabricated on silicon substrates (n-type) using chemical solution deposition with YMnO3 as an oxide layer. Electrical properties of MOS capacitor have been investigated with frequency dependence capacitance-voltage (C-V) characterization. The surface morphology of deposited layer was studied using the Atomic Force Microscopy (AFM). Hysteresis in the C-V loop and change in the values of Cminimum were described by a charge trap mechanism in the multiferroic oxide layer of MOS devices. While anomalous behavior in saturation capacitance in the inversion as well as in accumulation region and a shift in threshold voltage (VT) were explained in the vicinity of frequency depended Debye length (LDebye).

  Info
Periodical
Pages
92-99
DOI
10.4028/www.scientific.net/JNanoR.42.92
Citation
J.H. Markna, D. Dhruv, K.N. Rathod, C. Savaliya, T.M. Shiyani, D. Pandya, A. D. Joshi, N.A. Shah, "Charge Trap Mechanism in Hybrid Nanostructured (YMnO3) Metal-Oxide-Semiconductor (MOS) Devices", Journal of Nano Research, Vol. 42, pp. 92-99, 2016
Online since
July 2016
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