An Advanced LOCOS-Process for the Sub-50 nm-Region Using Low-Stress PECVD-Silicon Nitrides
|Periodical||Journal of Nano Research (Volume 6)|
|Main Theme||Journal of Nano Research Vol. 6|
|Citation||Klaus T. Kallis et al., 2009, Journal of Nano Research, 6, 23|
|Online since||June, 2009|
|Authors||Klaus T. Kallis, L.O. Keller, H.L. Fiedler|
|Keywords||Nanostructure, CMOS Process, Low Stress, Nitride, PECVD, Sub-50 nm-Dimensions|
The standard Local Oxidation of Silicon (LOCOS) technique uses different oxidation rates of silicon and Low Pressure Chemical Vapour Deposited (LPCVD) silicon nitride in steam ambient to structure the field oxide. Due to different coefficients of thermal expansion a pad oxide is needed at the boundary layer to prevent stress from the substrate. This leads to a lateral diffusion of oxygen, also known as “birds beak”, which limits the minimum structure size to a few 100 nm . When scaling down to this dimension, the Shallow Trench Isolation (STI) has become the standard isolation technique for fabrication of high-performance semiconductors to allow a high package density. Unfortunately the STI-process uses Chemical Mechanical Polishing (CMP) which increases the process complexity and leads to high costs. Therefore a new method which uses a low stress Plasma Enhanced Chemical Vapour Deposited (PECVD) silicon nitride without a pad oxide at the boundary layer will be presented in this paper.