Passivation crack is one of the main failures of micro-electronics. And the IC interconnect has a large varying range values comparing with its geometry size. In this paper, the influence of geometry values of micro-structures of IC packages on passivation cracking is studied by maximum principal stress theory using a certain 2D FEM model with different design geometry parameters, pitch of lines, width of line, thickness of epoxy, thickness of dielectric layer and the Aluminum yielding stress (following as “d”, “w”, “t_epo”, “t_Teos” and “sy_al” respectively). For different critical process step, here the final process temperature is acted as a representative parameter to analyze its impact. Furthermore, Response Surface Model (RSM) of principal stress is established using any two design parameters. Results show that width of line, thickness of dielectric layer and the Aluminium yielding stress will have great influence on passivation cracking while other parameters having little impact.