Substrate transfer technology for SOI and non-SOI single-crystalline silicon wafers was demonstrated allowing for high-performance low-power RF applications. 3D deformable electronics could be realized by vertically thinning and laterally partitioning of the silicon substrate on sub-millimeter scale. By varying the partition dimensions and the geometry of connecting bridges, the level of acceptable deformations can be controlled. The targeted applications of this technology are wireless ID tags and sensor networks. The mechanical properties such as crack, interfacial delamination are critical to reach the flexible substrate. In this contribution, results of our work on mechanical reliability issues of poly- and single crystalline silicon on ultra-thin polyimide substrates are presented. To improve reliability, square and hexagonal segmentation with different size is applied to the silicon layer before it is transferred onto an ultra-thin polyimide substrate using wafer-to-wafer substrate transfer technique based on a temporary glass carrier. Generation of cracks within the silicon and dielectric layers is then studied under controlled bending and tensile loads. The formation of cracks is studied experimentally using specially for this purpose designed bending and tensile tools. Ultra-thin interfacial delamination are also focused in this work by experimental and FE simulation method. A new test setup is designed for mixed mode bending testing which has capacity to observation specimen and recording the crack length and crack opening by microscope. The critical energy release depended on mixed angle can be reach by combination experimental data with FEM simulation.