Paper Title:
Dynamic Partition of Shared Cache for Multi-Thread Application in Multi-Core System
  Abstract

In a chip-multiprocessor with a shared cache structure , the competing accesses from different applications degrade the system performance.The accesses degrade the performance and result in non-predicting executing time. Cache partitioning techniques can exclusively partition the shared cache among multiple competing applications. In this paper, the authors design the framework of Process priority-based Multithread Cache Partitioning(PP-MCP),a dynamic shared cache partitioning mechanism to improve the performance of multi-threaded multi-programmed workloads. The framework includes a miss rate monitor , called Application-oriented Miss Rate Monitor (AMRM) , which dynamically collect s miss rate information of multiple multi-threaded applications on different cache partitions , and process priority-based weighted cache partitioning algorithm ,which extends traditional miss rate oriented cache partition algorithms.The algorithm allocates Cache in sequence of the value of the process priority and it ensures that the highest priority process will get enough Cache space; and the applications with more threads tend to get more shared cache in order to improve t he overall system performance. Experiments show that PP-MCP has better IPC throughput and weighted speedup. Specifically , for multi-threaded multi-programmed scientific computing workloads , PP-MCP-1 improves throughput by up to 20% and on average 10 % over PP-MCP-0.

  Info
Periodical
Key Engineering Materials (Volumes 439-440)
Edited by
Yanwen Wu
Pages
1587-1594
DOI
10.4028/www.scientific.net/KEM.439-440.1587
Citation
S. Li, F. Wu, "Dynamic Partition of Shared Cache for Multi-Thread Application in Multi-Core System", Key Engineering Materials, Vols. 439-440, pp. 1587-1594, 2010
Online since
June 2010
Authors
Export
Price
$32.00
Share

In order to see related information, you need to Login.

In order to see related information, you need to Login.

Authors: Shuo Li, Gao Chao Xu, Yu Shuang Dong, Feng Wu
Abstract:With the development of microelectronics technology, Chip Multi-Processor (CMP) or multi-core design has become a mainstream choice for major...
1223
Authors: Lei Yu, Zhi Yong Liu, Dong Rui Fan, Yi Ke Ma, Feng Long Song, Xiao Chun Ye, Wei Zhi Xu
Abstract:With the development of the computing ability of many-core processor, the acceleration of parallel programs on many-core has become the...
1226
Authors: Pei Xiang Yan, Jiang Jiang, Xian Ju Yang, Min Xuan Zhang
Chapter 2: Network & Control
Abstract:Capacity sharing is efficient for private L2 caches to utilize cache resources in chip multiprocessors. We propose a probabilistic sharing...
119
Authors: Juan Fang, Hong Bo Zhang
Chapter 7: Computer Engineering, Software, Communication and Data Processing
Abstract:The “Memory Wall” problem has become a bottleneck for the performance of processor, and on-chip multiprocessor(CMP) aggravates the memory...
253
Authors: Shuo Li, Gao Chao Xu, Xiao Lin Qiao, Feng Wu
Chapter 18: Development Computer Applications in Industry, Networks Applications
Abstract:The chip-multiprocessor (CMP) have been main stream of current processors, and it integrates the multi-core into the chip so that it can make...
2802