Flip-flops are main logic cells in digital systems, thus power-efficient designs are essential for micro systems, where ultra low-power hardware is demanded. This paper presents physical implementation and manufacture of adiabatic flip-flops based on CPAL (Complementary Pass-transistor Adiabatic Logic) circuits. The two mode-10 adiabatic counters based on four-phase and two-phase CPAL circuits have been implemented. For comparison, a conventional mode-10 counter using static CMOS circuits has also been embedded in a test chip. Full-custom layouts are drawn, and full parasitic extraction is done. The post-layout simulations are carried out using HSPICE. The chip has been fabricated with Chartered 0.35um process and tested.