Paper Title:
Near-Threshold Flip-Flops Using Clocked Adiabatic Logic in Nanometer CMOS Processes
  Abstract

This paper presents adiabatic flip-flops operating on near-threshold supply voltages. The near-threshold adiabatic flip-flops and sequential circuits are realized with improved CAL (Clocked Adiabatic Logic) circuits using a single-phase power clock. An auxiliary clock generator is used to obtain the non-overlap sinusoidal auxiliary signal pair. A near-threshold mode-10 counter is implemented. All circuits are simulated using Predictive Technology Model (PTM) 45nm process. The near-threshold adiabatic circuits attain large energy savings over a wide range of frequencies, as compared with conventional static CMOS logic circuits.

  Info
Periodical
Key Engineering Materials (Volumes 460-461)
Edited by
Yanwen Wu
Pages
837-842
DOI
10.4028/www.scientific.net/KEM.460-461.837
Citation
H. Y. Ni, J. P. Hu, "Near-Threshold Flip-Flops Using Clocked Adiabatic Logic in Nanometer CMOS Processes", Key Engineering Materials, Vols. 460-461, pp. 837-842, 2011
Online since
January 2011
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