Paper Title:
A High Throughput GALS Wrapper with Virtual Channels
  Abstract

A novel high throughput globally asynchronous locally synchronous wrapper is proposed to improve the network interface performance of network on chip. To prevent the occurrence of data sampling error, both the sender and receiver wrapper use the pausable clocking scheme to stop the clock when data come. The VC is based on Muller pipeline and chosen by the VC selector in the circuit. This wrapper can avoid the comparison between read pointer and write pointer in conventional design scheme and can increase the throughput. Simulations were based on SMIC 0.18um CMOS technology, and the sender wrapper and receiver wrapper have the throughput as high as 810Mflit/s and 820Mflit/s respectively.

  Info
Periodical
Key Engineering Materials (Volumes 474-476)
Edited by
Garry Zhu
Pages
2171-2176
DOI
10.4028/www.scientific.net/KEM.474-476.2171
Citation
S. T. Shang, X. G. Guan, Y. T. Yang, "A High Throughput GALS Wrapper with Virtual Channels", Key Engineering Materials, Vols. 474-476, pp. 2171-2176, 2011
Online since
April 2011
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Price
$32.00
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