Paper Title:
Design and System-Level Simulation of a Novel On-Chip Test Based on Macromodels
  Abstract

The methods of on-chip integrated testing have a wide application with the development of the study for MEMS materials properties measurement in microscale. A novel on-chip integrated micro-tensile testing system is designed through system-level simulation based on macromodels to measure the fracture strength and fatigue mechanical properties of polysilicon thin films. The structure of testing instrument consists of V-beam electrothermal actuator, differential capacitance sensor, supporting spring and specimen. The capacitance signal is sensed and controlled by a second sigma-delta modulator circuit. The analytic macromodel of polysilicon thin film specimen considering geometric nonlinearity and the numerical reduced-order model of V-beam electrothermal actuator based on Krylov subspace projection are created separately and described in the MAST hardware language. The mechanical structure dimension size and circuit components parameters are determined and optimized according to system-level simulation. The computing result has shown that the self-build macromodels and the on-chip integrated test system are efficient and reliable.

  Info
Periodical
Edited by
Xiaohao Wang
Pages
38-42
DOI
10.4028/www.scientific.net/KEM.483.38
Citation
L. Guan, J. L. Gao, J. K. Chu, "Design and System-Level Simulation of a Novel On-Chip Test Based on Macromodels", Key Engineering Materials, Vol. 483, pp. 38-42, 2011
Online since
June 2011
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$32.00
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