Paper Title:
A High-Performance Interface ASIC for Quartz Rate Sensor
  Abstract

In this work, an ASIC interface for quartz rate sensor (QRS) is introduced. Based on 0.6μm 18V N-well CMOS process, it is the first to be realized in the domestic. This chip has a minimized size of 5×4.4mm2. Compared with traditional interface constructed by separate devices, such interface implemented with integrated circuits is advantageous in size and power consumption. This satisfies the requirements of miniature and low power consumption in space industry and military domain. The test results show that this interface features low noise, high linearity, and stable operation. Integrated with the sensor, the entire system presents high performance in short term bias stability, nonlinearity, output noise, bias variation over temperature, and power consumption.

  Info
Periodical
Edited by
Xiaohao Wang
Pages
471-474
DOI
10.4028/www.scientific.net/KEM.483.471
Citation
W. P. Chen, Q. Y. Wang, L. Yin, Z. P. Zhou, "A High-Performance Interface ASIC for Quartz Rate Sensor", Key Engineering Materials, Vol. 483, pp. 471-474, 2011
Online since
June 2011
Keywords
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