Paper Title:
A Four-Quadrant Analog Multiplier Based on CMOS Source Coupled Pair
  Abstract

A novel structure for CMOS four-quadrant analog multiplier is presented. The multiplier is based on the square law of MOSFET. To enlarge the input impedance and improve the linearity, CMOS source coupled pair was employed. Also active attenuator was used to enhance the input range. Compared with the traditional multipliers based on Gilbert cell, the proposed circuit features high linearity, high input range. Circuit simulation using HSPICE with 0.5μm CMOS technology shows that under ±2.5V supply the proposed multiplier provides linear range of more than 50% of the voltage supply, THD is 0.3% at 100kHz and 0.8% at 1MHz, -3dB bandwidth is 2.5MHz, and the power consumption is 5mW.

  Info
Periodical
Edited by
Xiaohao Wang
Pages
487-491
DOI
10.4028/www.scientific.net/KEM.483.487
Citation
W. P. Chen, T. Y. Wang, H. L. Xu, X. W. Liu, "A Four-Quadrant Analog Multiplier Based on CMOS Source Coupled Pair", Key Engineering Materials, Vol. 483, pp. 487-491, 2011
Online since
June 2011
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