Paper Title:
Formal Verification of Embedded Systems Using the Alvis Approach
  Abstract

Embedded systems are usually characterized by time-critical reactions and increased complexity. Because it is usually impossible to correct a system bug by simply uploading of a new version of a system software or firmware, a system behavior should be verified in a formal manner. The Alvis approach presented in this paper is able to verify the system behavior, by specifying the border between a developed embedded system and its environment. The means to move the border is then proposed, which allows the designer to create a formal representation for selected parts of a model only.

  Info
Periodical
Edited by
Daizhong Su, Kai Xue and Shifan Zhu
Pages
209-212
DOI
10.4028/www.scientific.net/KEM.486.209
Citation
L. Kotulski, M. Szpyrka, "Formal Verification of Embedded Systems Using the Alvis Approach", Key Engineering Materials, Vol. 486, pp. 209-212, 2011
Online since
July 2011
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Price
$35.00
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