The density of interface traps (Dit) in thermally oxidized SiC is unacceptably high for MOS device fabrication. The most severe problem is posed by the extremely high concentration of slow acceptor states near the conduction band edge of 4H-SiC. These states are attributed to near interface traps originating from (probably intrinsic) defects in the oxide. Here a systematic theoretical search is presented for possible defects in the oxide with an appropriate acceptor level. Supercell calculations using a hybrid functional approach (and resulting in a correct gap) on defects in alpha-quartz exclude the oxygen vacancy and the oxygen interstitial, as possible candidates. In contrast, these calculations predict interstitial silicon to have an acceptor level in the appropriate range. The carbon interstitial in silica has an acceptor level somewhat deeper than that. Occupation of these levels give rise to significant rearrangement of the environment, leading to a more extended defect structure.