4H-SiC MOSFET devices with low temperature dry thermal oxidation (1050 °C 1 h) and TEOS plasma enhanced CVD deposited oxides on 4H-SiC substrates have been analysed in this paper. MOSFET transistors have been fabricated on the 4H-SiC (0001) Si face. The mobility improvement (up to 38-45 cm2/Vs) is remarkable compared with standard oxidation (<10 cm2/Vs). In addition, very high (but controversial) field-effect mobilities of around 216 cm2/Vs have also been extracted for MOSFETs fabricated on the (11-20) face. Taking into account the threshold voltage and the sub-threshold slope (S), we can see that we have three different ways to increase the mobility. First, by using (11-20) face material as already proposed. Second, by reducing the interface trap density as done with the low temperature thermal oxidation plus deposited oxide. And third, under the most favorable conditions with adequate TEOS deposition conditions. In this last case, the mobility improvement seems to be related with the gate current leakage more than (or together with) an interface traps reduction of the gate insulator.