This paper reports recent progress in the development of a vertical JFET, the purely vertical JFET based on trenched-and-implanted vertical JFET (TI-VJFET) approach that eliminates the need of epitaxial regrowth at middle of device fabrication and the need of a merged lateral JFET to control the vertical JFET. Different structures have been designed to target breakdown voltages ranging from 600V to 1.2kV. Vertical channel width uniformity has been studied, showing the feasibility of achieving below 0.1um variation for reasonably flat wafers of good thickness uniformity. Pitch size of the designs has been reduced compared to early report. Gate trench width has been reduced from 3.8um to 2.3um, aimed at increasing the device current capability. Fabricated device cells have been tested and packaged into multi-cell 30A TI-VJFETs which have been characterized of DC and switching characteristics at room and elevated temperatures. Very fast current rise/fall times of <10ns were observed from RT to 200°C. PSpice model for TI-VJFET has been developed and applied to the performance prediction of 3-phase SiC power inverter, suggesting a high efficiency 97.7% at 200°C junction temperature without using soft-switching scheme. Preliminary experimental demonstration of a PWM-controlled three-phase inverter based on SiC TI-VJFET power board is reported.