Design, Fabrication and Application of 4H-SiC Trenched-and-Implanted Vertical JFETs

Alexandrov, Petre; Zhao, Jian H.; Li, Larry X.; Li, Yu Zhu; Sheng, Kuang; Lebron-Velilla, Ramon

Get full access here Site/IP Subscriptions Log in

My Cart

Advanced Search

Paper Titles

Fabrication of 4H-SiC Floating Junction Schottky Barrier Diodes (Super-SBDs) and their Electrical Properties, p.1175
Optimization of a SiC Super-SBD Based on Scaling Properties of Power Devices, p.1179
Fast Switching (41 MHz), 2.5 mΩ•cm², High Current 4H-SiC VJFETs for High Power and High Temperature Applications, p.1183
10 kV, 87 mΩcm² Normally-Off 4H-SiC Vertical Junction Field-Effect Transistors, p.1187
Design, Fabrication and Application of 4H-SiC Trenched-and-Implanted Vertical JFETs, p.1191
Analytical Modelling of I-V Characteristics for 4H-SiC Enhancement Mode VJFET, p.1195
Design Considerations of a New 4H-SiC Enhancement-Mode Lateral Channel Vertical JFET for Low-Loss Switching Operation, p.1199
Low On-Resistance in 4H-SiC RESURF JFETs Fabricated with Dry Process for Implantation Metal Mask, p.1203
SiC Smart Power JFET Technology for High-Temperature Applications, p.1207

Home > Materials Science Forum > Silicon Carbide and Related Materials 2005 > Design, Fabrication and Application of 4H-SiC...

Paper Title:

Design, Fabrication and Application of 4H-SiC Trenched-and-Implanted Vertical JFETs

Periodical	Materials Science Forum (Volumes 527 - 529)
Main Theme	Silicon Carbide and Related Materials 2005
Edited by	Robert P. Devaty, David J. Larkin and Stephen E. Saddow
Pages	1191-1194
DOI	10.4028/www.scientific.net/MSF.527-529.1191
Citation	Jian H. Zhao et al., 2006, Materials Science Forum, 527-529, 1191
Online since	October, 2006
Authors	Jian H. Zhao, Petre Alexandrov, Yu Zhu Li, Larry X. Li, Kuang Sheng, Ramon Lebron-Velilla
Keywords	High Temperature, High-Efficiency, JFET, Low Resistance
Price	US$ 28,-

View full size

Abstract

This paper reports recent progress in the development of a vertical JFET, the purely vertical JFET based on trenched-and-implanted vertical JFET (TI-VJFET) approach that eliminates the need of epitaxial regrowth at middle of device fabrication and the need of a merged lateral JFET to control the vertical JFET. Different structures have been designed to target breakdown voltages ranging from 600V to 1.2kV. Vertical channel width uniformity has been studied, showing the feasibility of achieving below 0.1um variation for reasonably flat wafers of good thickness uniformity. Pitch size of the designs has been reduced compared to early report. Gate trench width has been reduced from 3.8um to 2.3um, aimed at increasing the device current capability. Fabricated device cells have been tested and packaged into multi-cell 30A TI-VJFETs which have been characterized of DC and switching characteristics at room and elevated temperatures. Very fast current rise/fall times of <10ns were observed from RT to 200°C. PSpice model for TI-VJFET has been developed and applied to the performance prediction of 3-phase SiC power inverter, suggesting a high efficiency 97.7% at 200°C junction temperature without using soft-switching scheme. Preliminary experimental demonstration of a PWM-controlled three-phase inverter based on SiC TI-VJFET power board is reported.