Paper Title:
Design Considerations of a New 4H-SiC Enhancement-Mode Lateral Channel Vertical JFET for Low-Loss Switching Operation
  Abstract

A new silicon carbide (SiC) enhancement-mode lateral channel vertical junction fieldeffect transistor (LC-VJFET), namely “source inserted double-gate structure (SID-gate) with a supplementary highly doped region (SHDR)”, was proposed for achieving extremely low power losses in high power switching applications. The proposed architecture was based on the combination of an additional source electrode inserted between two adjacent surface gate electrodes and a unique SHDR in the vertical channel region. Two-dimensional numerical simulations for the static and resistive switching characteristics were performed to analyze and optimize the SiC LCVJFET structures for this purpose. Based on the simulation results, the excellent performance of the proposed structure was compared with optimized conventional structures with regard to total power losses. Finally, the proposed structure showed about a 20 % reduction in on-state loss (Pon) compared to the conventional structures, due to the effective suppression of the JFET effect. Furthermore, the switching loss (Psw) of the proposed structure was found to be much lower than the results of the conventional structures, about a 75 % ~ 95 % reduction, by significantly reducing both input capacitance (Ciss) and reverse transfer capacitance (Crss) of the device.

  Info
Periodical
Materials Science Forum (Volumes 527-529)
Edited by
Robert P. Devaty, David J. Larkin and Stephen E. Saddow
Pages
1199-1202
DOI
10.4028/www.scientific.net/MSF.527-529.1199
Citation
Y.C. Choi, H. Y. Cha , L. F. Eastman, M. G. Spencer, "Design Considerations of a New 4H-SiC Enhancement-Mode Lateral Channel Vertical JFET for Low-Loss Switching Operation", Materials Science Forum, Vols. 527-529, pp. 1199-1202, 2006
Online since
October 2006
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$32.00
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