Paper Title:
Inherently Safe Resonant Reset Forward Converter Using a Bias-Enhanced SiC JFET
  Abstract

The power junction field effect transistor (JFET) is the second most mature SiC device, after the SiC Schottky diode, and is commonly associated with normally on functionality; but this feature is often viewed problematically for off-line dc-to-dc converter applications. Two inherently safe, single-switch dc-dc converter designs have been developed that put into practice pure SiC JFET devices (i.e., without cascoded devices) that possess enhancement-mode functionality and bias-enhanced blocking. These ‘Quasi-Off’ devices are designed to block half of the rated blocking voltage at zero gate bias and achieve full rated blocking voltage with a modest negative bias, typically between 0 and -5 V. Inherent safety is provided by utilizing the enhancement mode functionality of these devices as well as appropriate gate driver design. Bias enhanced blocking matches the dynamic stress encountered by modern high-frequency power supply topologies to the ratings of the device while recognizing that the larger dynamic stress is typically encountered only when the power supply (and especially the gate driver) is functioning properly.

  Info
Periodical
Materials Science Forum (Volumes 527-529)
Edited by
Robert P. Devaty, David J. Larkin and Stephen E. Saddow
Pages
1211-1214
DOI
10.4028/www.scientific.net/MSF.527-529.1211
Citation
R. L. Kelley, T. Brignac, M. S. Mazzola, J. B. Casady, "Inherently Safe Resonant Reset Forward Converter Using a Bias-Enhanced SiC JFET", Materials Science Forum, Vols. 527-529, pp. 1211-1214, 2006
Online since
October 2006
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Price
$32.00
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