Paper Title:
4H-SiC DMOSFETs Processed Using Graphite Capped Implant Activation Anneal
  Abstract

Results of a 1200V 4H-SiC vertical DMOSFET based on ion implanted n+ source and pwell regions are reported. The implanted regions are activated by way of a high temperature anneal (1675°C for 30 min) during which the SiC surface is protected by a layer of graphite. Atomic force microscopy shows the graphite to effectively prevent surface roughening that otherwise occurs when no capping layer is used. MOSFETs are demonstrated using the graphite capped anneal process with a gate oxide grown in N2O and show specific on-resistance of 64 mW×cm2, blocking voltage of up to 1600V and leakage current of 0.5–3 ´10-6 A/cm2 at 1200V. The effective nchannel mobility was found to be 1.5 cm2/V×s at room temperature and increases as temperature increases (2.8 cm2/V×s at 200°C).

  Info
Periodical
Materials Science Forum (Volumes 527-529)
Edited by
Robert P. Devaty, David J. Larkin and Stephen E. Saddow
Pages
1265-1268
DOI
10.4028/www.scientific.net/MSF.527-529.1265
Citation
J. B. Fedison, C. S. Cowen, J. L. Garrett, E.T. Downey, J. W. Kretchmer, R.L. Klinger, H.C. Peters, J. B. Tucker, K. Matocha, L.B. Rowland, S. Arthur, "4H-SiC DMOSFETs Processed Using Graphite Capped Implant Activation Anneal", Materials Science Forum, Vols. 527-529, pp. 1265-1268, 2006
Online since
October 2006
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$32.00
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