Paper Title:
Techniques for Minimizing the Basal Plane Dislocation Density in SiC Epilayers to Reduce Vf Drift in SiC Bipolar Power Devices
  Abstract

Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.

  Info
Periodical
Materials Science Forum (Volumes 527-529)
Edited by
Robert P. Devaty, David J. Larkin and Stephen E. Saddow
Pages
141-146
DOI
10.4028/www.scientific.net/MSF.527-529.141
Citation
J. J. Sumakeris, P. Bergman, M. K. Das, C. Hallin, B. A. Hull, E. Janzén, H. Lendenmann, M. J. O'Loughlin, M. J. Paisley, S. Y. Ha, M. Skowronski, J. W. Palmour, C. H. Carter Jr., "Techniques for Minimizing the Basal Plane Dislocation Density in SiC Epilayers to Reduce Vf Drift in SiC Bipolar Power Devices", Materials Science Forum, Vols. 527-529, pp. 141-146, 2006
Online since
October 2006
Export
Price
$32.00
Share

In order to see related information, you need to Login.

In order to see related information, you need to Login.

Authors: Mrinal K. Das, Joseph J. Sumakeris, Brett A. Hull, Jim Richmond
Abstract:The PiN diode is an attractive device to exploit the high power material advantages of 4H-SiC. The combination of high critical field and...
1329
Authors: Joseph J. Sumakeris, Brett A. Hull, Michael J. O'Loughlin, Marek Skowronski, Vijay Balakrishna
Abstract:We detail a comprehensive approach to preparing epiwafers for bipolar SiC power devices which entails etching the substrate, growing a...
77
Authors: Birgit Kallinger, Bernd Thomas, Sebastian Polster, Patrick Berwian, Jochen Friedrich
Abstract:Basal Plane Dislocations (BPDs) in SiC are thought to cause degradation of bipolar diodes with blocking voltages > 2kV by triggering the...
299
Authors: Hai Zheng Song, Tangali S. Sudarshan
Chapter 2: SiC Epitaxial Growth
Abstract:An optimized molten KOH-NaOH eutectic etching method is developed to reveal defects in highly n-doped SiC substrates and to pre-treat the...
125
Authors: Chiharu Ota, Johji Nishio, Kazuto Takao, Takashi Shinohe
Chapter 5: Devices and Circuits
Abstract:In this paper, we found origin of VF degradation of SiC bipolar devices other than a basal plane dislocation (BPD) in the SiC...
851