Paper Title:

Ion Implanted p+/n Diodes: Post-Implantation Annealing in a Silane Ambient in a Cold-Wall Low-Pressure CVD Reactor

Periodical Materials Science Forum (Volumes 527 - 529)
Main Theme Silicon Carbide and Related Materials 2005
Edited by Robert P. Devaty, David J. Larkin and Stephen E. Saddow
Pages 819-822
DOI 10.4028/www.scientific.net/MSF.527-529.819
Citation Fabio Bergamini et al., 2006, Materials Science Forum, 527-529, 819
Online since October, 2006
Authors Fabio Bergamini, Shailaja P. Rao, Antonella Poggi, Fabrizio Tamarri, Stephen E. Saddow, Roberta Nipoti
Keywords Atomic Force Microscope (AFM), Ion Implantation, p+/n Junction Diode, Post Implantation Annealing, Silane
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Abstract

This work reports the realization and characterization of 4H-SiC p+/n diodes with the p+ anodes made by Al+ ion implantation at 400°C and post-implantation annealing in silane ambient in a cold-wall low-pressure CVD reactor. The Al depth profile was almost box shaped with a height of 6×1019 cm-3 and a depth of 160 nm. Implant anneals were performed in the temperature range from 1600°C to 1700°C. As the annealing temperature was increased, the silane flow rate was also increased. This annealing process yields a smooth surface with a roughness of the implanted area of 1.7 - 5.3 nm with increasing annealing temperature. The resistivity of the implanted layer, measured at room temperature, decreased for increasing annealing temperatures with a minimum value of 1.4 0-cm measured for the sample annealed at 1700°C. Considering only the current-voltage characteristic of a diode that could be modeled as an abrupt p/n junction within the frame of the Shockley theory, the diode process yield and the diode leakage current decreased, respectively, from 93% to 47% and from 2×10-7 Acm-2 to 1×10-8 Acm-2 at 100 V reverse bias, for increasing post implantation annealing temperature.