Electron mobility for the silicon-based devices is one of the most important parameters, which determine the behavior of components. Mobility depends on silicon purity, doping level, presence of lattice defects and electric field in the particular device. These influences are particularly important for the nano-scaled devices since it is much more difficult to control the thickness of the active layer, uniformity of impurity doping and appearance of parasitic bipolar devices and capacitances. We have investigated a relationship between the electron mobility for the silicon based PD (Partially Depleted) SOI (Silicon On Insulator) NMOS (n-type Metal Oxide Semiconductor) Devices and the related kink effect, which appears as a consequence of the charge accumulation at the interface of the Buried Oxide. We relate PD SOI NMOS Device technology parameters to the kink effect and we propose a guiding line for alleviating this effect.