Paper Title:
Analysis of Novel Packaging Techniques for High Power Electronics in SiC
  Abstract

A novel high temperature wire bondless packaging technique is numerically investigated in this paper. Extraction of device effective resistivity with temperature from numerical characteristics of 1.2kV 4H-SiC MOSFETs at a current density of 400A/cm2 have demonstrated a T−2 temperature dependence. Electro-thermal finite element analysis (FEA) of 1.2kV 4H-SiC MOSFETs sandwiched between two etched direct-bonded-copper substrate tiles has been performed. The thermal resistance of the ceramic sandwich package shows a 75% reduction in thermal resistance compared to conventional wire bonded assemblies. Mechanical analysis of the assembly has been used to investigate the residual stresses in the SiC dies at room temperature, which are then alleviated at higher temperatures during device operation. Mismatch of the expansion coefficients of the auxiliary materials in the assembly result in elevated stresses at full load operation, however these are well below the tensile strength of the respective materials and hence do not compromise the mechanical integrity of the package.

  Info
Periodical
Materials Science Forum (Volumes 556-557)
Edited by
N. Wright, C.M. Johnson, K. Vassilevski, I. Nikitina and A. Horsfall
Pages
971-974
DOI
10.4028/www.scientific.net/MSF.556-557.971
Citation
S.J. Rashid, C. M. Johnson, F. Udrea, A. Mihaila, G. Amaratunga, R. K. Malhan, "Analysis of Novel Packaging Techniques for High Power Electronics in SiC", Materials Science Forum, Vols. 556-557, pp. 971-974, 2007
Online since
September 2007
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Price
$32.00
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