Scaling of CMOS structures through the deep sub-micron range and into the nano-scale range (< 100 nm) has posed a number of difficult problems for processing technology. One main technological approach has been to improve the uniformity and conformality of deposited layers. As the Atomic Layer Deposition (ALD) has already demonstrated that it can overcome many of the limitations of current film deposition techniques, it seems to be the solution for very conformal layers of high quality on severe topography. The ALD method has been developed already in the 1970’s by Tumo Suntola and co-workers [1-4]. However, it has been in the past a rather unused method in the semiconductor industry. This has recently changed. During the last couple of years, the large semiconductor companies have spent a lot of effort in the utilization of ALD, but until now a production worthy ALD tool with low ‘Cost-of-Ownership’ (CoO) numbers was not available. One reason for the late introduction of ALD is that the method is rather slow compared with the state of art methods like CVD, PECVD and PVD. Nevertheless, due to the outstanding properties of the ALD technique, the drawback of slow deposition rate may be balanced by the parallel processing of many wafers in semiconductor furnaces, as described here.