High integration, density and complexity are essential in electronic products such as compact and light mobile phone recently. A new type of development for component and material is also needed. In the PCB design aspect, a technique such as pad on via, trying to keep up with the demand for compact and slim products, is commonly used. In a response to increased pressure from these situations, an enhanced ability on reliability of electronic products is gradually needed. The high cost and risk, however, are higher and higher for the assurance in the reliability. We made a procedure which can evaluate a solder joint reliability on the product development phase. Furthermore, we've pursued a development process for preventing failure as we analyzed the failure mode from predicting the causes of the failure more precisely. In this study, focusing on the joint reliability of the solder interconnection between CSP and pad on via, we have passed through a test procedure as follows. First, making samples applied with high integrated circuit (CSP: 0.65 pitch, via hole size: 165um, solder: Sn-3.0Ag-0.5Cu). Second, operating the thermal cycling experiment (- 45°C~+125°C, 30min/cycle) to find a failure of the test specimen with an electrical method. Third, observation the non-destructive X-ray microscopy and the metallographic cross-sectioning. Fourth, simulation of the finite element model and deformation analysis. Fifth, completion the modeling of the failure mode. Lastly, prediction a lifetime of the solder joint.